Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!cs.utexas.edu!uunet!dg!rec From: rec@dg.dg.com (Robert Cousins) Newsgroups: comp.arch Subject: Re: 88k needs fewer instructions than VAX. (Was: Compiling - RISC vs. CISC) Message-ID: <201@dg.dg.com> Date: 14 Jul 89 14:12:46 GMT References: <13976@lanl.gov> <199@dg.dg.com> <28471@ames.arc.nasa.gov> <200@dg.dg.com> Reply-To: uunet!dg!rec (Robert Cousins) Organization: Data General, Westboro, MA. Lines: 72 In article zs01+@andrew.cmu.edu (Zalman Stern) writes: >> I wrote: >> Hugh, I agree that Dhrystone is one benchmark in a whole field of >> benchmarks. However, I feel comfortable drawing a simple conclusion >> from this result: It is not clear that a CISC processor will take >> FEWER INSTRUCTIONS to solve a problem than a RISC processor. In some >> cases RISCs may require fewer instructions. > [text deleted] > >As far as I can tell, Robert Cousins statement was that he was surprised >by the fact that for their 88k machine, . . . . > I apparently did not make my point clear. Let me try it again: There has been a somewhat widespread use do the term "Dhrystone MIPS" in the industry. This is commonly linked to some actual measure of performance. There has been fast and loose use of this term interchangeably with the other relatively useless measure of performance MIPS. Not only are these two measures not the same but they are only of limited applicability. The example I gave earlier where Dhrystone MIPS > Raw MIPS disproves the similarity. On a slightly different front, I think this inequality can be used as anecdotal evidence that perhaps the traditional belief that the # CISC instructions < # RISC instructions to do the same job does not always hold true. >Another problem here is that the term RISC is as bogus as the above >usage of the MIPS abbreviation. The 88k differs from other processors >described as RISC in that it has addressing modes for its load and store ^^^^^^^^^^^^^^^^ >instructions. There are probably interesting discussion to be had as to >code density and architectural features (i.e. address modes), but I >don't have any data so I'll shut up. > >Sincerely, >Zalman Stern >Internet: zs01+@andrew.cmu.edu Usenet: I'm soooo confused... >Information Technology Center, Carnegie Mellon, Pittsburgh, PA 15213-3890 The addressing modes for the 88100 loads and stores are: Immediate Register Indirect with immediate index Register Indirect with index Register Indirect with scaled index In the immediate form, a 10 or 16 bit (depending upon the instruction) value is used as an operand. In the Register Indirect with Immediate form, a 16 bit unsigned (yes, unsigned) value is added to the contents of the register to form the address. In the Register Indirect with Index form, two registers are added together to form the effective address. In the Register Indirect with Scaled Index form, two registers are added together after one is shifted left 0 to 3 bits. All load instructions take the same amount of time and are all 4 bytes long. If this makes the 88K non-RISC, then I must ask you to produce a true RISC machine for reference which has no non-RISC features. Robert Cousins Dept. Mgr, Workstation Dev't. Data General Corp. Speaking for myself alone.