Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!ucsd!ames!uhccux!munnari.oz.au!comp.vuw.ac.nz!dsiramd!ray
From: ray@dsiramd.dsir.govt.nz (Ray Brownrigg)
Newsgroups: comp.arch
Subject: Re: 88k needs fewer instructions than VAX. (Was: Compiling - RISC vs. CISC)
Message-ID: <386@dsiramd.dsir.govt.nz>
Date: 18 Jul 89 03:00:55 GMT
References: <13976@lanl.gov> <199@dg.dg.com> <28471@ames.arc.nasa.gov> <200@dg.dg.com> <EYjByca00Vs8ILNl8K@andrew.cmu.edu> <201@dg.dg.com> <23375@sprint.mips.COM>
Reply-To: ray@dsiramd.dsir.govt.nz (Ray Brownrigg)
Organization: DSIR Applied Mathematics Division, Wellington, NZ
Lines: 27

In article <23375@sprint.mips.COM> hawkes@mips.COM (John Hawkes) writes:
>					"Dhrystone MIPS" have nothing
>whatsoever to do with "Raw MIPS".  I define "Raw MIPS" to be the number of
>millions of native instructions per second that a system executes for a given
>application. 

However "Dhrystone MIPS" still has not been accurately defined.

Dhrystone MIPS is a shorthand term for "(Dhrystones per second)/1757"
where 1757 is the 'current' value (i.e. whatever value the author choses to
use) for Dhrystones/sec on a VAX/780. Thus the term means the speed (relative
to a VAX/780) of executing the Dhrystone benchmark.

Note that the Dhrystone benchmark measures "*Dhrystone instructions* per
second", and so in fact a VAX/780 runs at ~0.00175 million Dhrystone
instructions per second, or .00175 Dhrystone Mips if you care to look at
it that way!

Of course a single Dhrystone 'instruction' has nothing at all to do with 
the architecture of a CPU, it is a concept designed purely for benchmarking
purposes.

-- 
Ray Brownrigg			domain: ray@dsiramd.dsir.govt.nz
Applied Maths Div, DSIR		ACSnet:	ray@dsiramd.nz[@munnari]
PO Box 1335			System:	OLIVETTI/AT&T 3B2/400B+, System V R3.0
Wellington, New Zealand			"unx -rul