Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!purdue!decwrl!polyslo!usc!bbn!clsib21!lpi!burn From: burn@lpi.UUCP (Don Burn) Newsgroups: comp.arch Subject: Re: Register pairing (Was: Compiling - RISC vs. CISC) Message-ID: <305@lpi.UUCP> Date: 14 Jul 89 14:12:11 GMT References: <2190@oakhill.UUCP> <13980@lanl.gov> <2199@oakhill.UUCP> Reply-To: burn@lpi.UUCP (Don Burn) Organization: Language Processors Inc., Framingham MA Lines: 41 In article zs01+@andrew.cmu.edu (Zalman Stern) writes: >By "register pairing" I assume you mean instructions which take an even >register specification and use the adjacent odd register as well. My >perusal of the MIPS R2000 book indicates that there are no such >instructions in that architecture. I believe this is also true of the >AMD 29000. I think its almost true of the SPARC, but it has 64 bit load >and store instructions from the integer unit's register file that >utilize register pairing. (As I understand it the main reason these >instructions were added to the SPARC was to speed up transferring >register windows to/from memory. It is probably reasonable to write a >compiler for SPARC that ignores these instructions and doesn't have to >worry about register pairing.) > >The only place I could find register pairing in the 88000 was in the >floating point instructions. This is a result of using one register file >for the integer and floating point units. (My knowledge of the 88000 is >limited, I have the user's manual, but I haven't read it in depth. I may >be wrong about this...) Most other "RISC" chips I know of have separate >integer and floating point register sets and avoid this problem. Funny the AMD 29000 manual in front of me says: "By convention, a double precision floating-point operand is contained in two consecutive general purpose registers,..." The i860 manual states: "When accessing 64-bit floating-point or integer values, the i860 Microprocessor uses an even/odd pair of registers" I loaned out my SPARC manual but the compilers we implemented use register pairs, I don't know about MIPS but since it like SPARC used the Weitek chip set which uses register pairs I wouldn't be suprised if they have pairs exposed. Finally for a limited set of instructions (shifts) the IBM RT uses pairs. Don Burn Project Leader, Code Generator Group The opinions are my own, my company just gets the code.