Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!tut.cis.ohio-state.edu!attctc!chasm
From: chasm@attctc.DALLAS.TX.US (Charles Marslett)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Extended memory board and RAM speed...
Summary: Magic inside the chips confuse us...
Message-ID: <8586@attctc.DALLAS.TX.US>
Date: 8 Jul 89 23:25:46 GMT
References: <5876@rpi.edu> <23080@iuvax.cs.indiana.edu>
Distribution: na
Organization: The Unix(R) Connection, Dallas, Texas
Lines: 25

In article <23080@iuvax.cs.indiana.edu>, bobmon@iuvax.cs.indiana.edu (RAMontante) writes:
> My understanding of waitstates is (still) weak, but if it really means
> just a second clock cycle in memory accesses, then 12MHz/1ws would
> be equivalent to 6MHz/0ws and 120ns chips would be adequate (but what
> does the machine already have??).  In any case, I can't imagine how
> faster-than-necessary chips would do you any good, as the machine will
> take as long as it takes to access memory regardless.

Actually, a normal (no-wait) memory access takes 2 wait states, so if you add
one wait state, it takes 50% longer, rather than twice as long.

This means that a 12 MHz 1 wait state machine actually has 250 ns to fetch
a word from memory.  The real problem in figuring out how fast the RAM has to
be is the time it takes to decode addresses and enable buffers (all that stuff
in the C&T or W/D chip sets).  They usually take 75-100 ns, so add that to
the access time and if it fits, it's probably OK.  Another "feature" of
RAM chips is they get slower when they have company (like people) -- RAM on
a large memory board will be slower than the same RAM chips on a smaller
memory board.

===========================================================================
Charles Marslett
STB Systems, Inc.  <== Apply all standard disclaimers
Wordmark Systems   <== No disclaimers required -- that's just me
chasm@attctc.dallas.tx.us