Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!tut.cis.ohio-state.edu!pt.cs.cmu.edu!b.gp.cs.cmu.edu!ralf
From: ralf@b.gp.cs.cmu.edu (Ralf Brown)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Extended memory board and RAM speed...
Message-ID: <5456@pt.cs.cmu.edu>
Date: 10 Jul 89 02:11:44 GMT
References: <5876@rpi.edu> <23080@iuvax.cs.indiana.edu>
Distribution: na
Organization: Carnegie-Mellon University, CS/RI
Lines: 17

In article <23080@iuvax.cs.indiana.edu> bobmon@iuvax.cs.indiana.edu (RAMontante) writes:
}My understanding of waitstates is (still) weak, but if it really means
}just a second clock cycle in memory accesses, then 12MHz/1ws would
}be equivalent to 6MHz/0ws and 120ns chips would be adequate (but what

Actually, a wait state means a *third* clock cycle.  8086's take four clocks
per memory access, which is slow enough that I've never heard of a PC or XT
with wait states (though I've seen a number advertised as having 0 wait 
states--some "feature"!).  80286's and 80386's take two clocks per memory
access, and the new 486 chip has a burst mode that can load the internal cache
at the rate of one memory read every clock cycle.

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