Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!leah!rpi!pawl3.pawl.rpi.edu!entropy
From: entropy@pawl.rpi.edu (Math Student from Hell)
Newsgroups: comp.lang.asm370
Subject: SVC 202 under CMS
Summary: Error return address
Message-ID: <6214@rpi.edu>
Date: 26 Jul 89 02:13:08 GMT
Sender: usenet@rpi.edu
Distribution: usa
Organization: Eaters of Wisdom
Lines: 30


	Under CMS, an SVC 202 instruction is followed by a four-byte
address which points at the place to which control returns in the event
of an error.

	I was recently made aware of this fact.  I was adding features
to our source-level debugger, and discovered that the 'disassemble'
feature was failing to disassemble instructions that followed SVC
202s.  Why?  Well, SVC is a two-byte instruction (opcode 10<64), and
after the disassembler disassembled the SVC, it looked two bytes
farther along for the next instruction and found garbage- the error
return address.

	It wasn't hard to patch it up and make a special case:  Just
check if the first word of the instruction is 0ACA, and if it is, the
instruction length is 6 bytes, not 2, but it occurred to me:  When IBM
first introduced the CMS SVC 202 call, it must have broken _every_
_single_ _disassembler_ in the entire world.

	Am I perceiving this wrong?  Is there a simple solution?  Can
someone show me that IBM did not perpetrate an utterly stupid,
gratuitously shoddy piece of design?  Or did they?  Why not, for
example, require register three or some such to be loaded with the
error return address?

	Truly, IBM moves in Strange and Mysterious ways.


    What a wonderful thing is the human brain; how I wish I possessed one.
Mark-Jason Dominus 	   entropy@pawl.rpi.EDU	     entropy@rpitsmts (BITnet)