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From: brooks@portia.Stanford.EDU (Michael Brooks)
Newsgroups: comp.unix.cray,sci.physics,comp.lsi
Subject: Re: GaAs CMOS in Cray-3 ?
Summary: MESFETS, enh and depl.
Keywords: Cray-3, GaAs, LSI, CMOS, hole mobility
Message-ID: <3892@portia.Stanford.EDU>
Date: 24 Jul 89 17:40:56 GMT
References: <7048@microsoft.UUCP>
Sender: Michael Brooks <brooks@Portia.stanford.edu>
Reply-To: brooks@Portia.Stanford.EDU (Michael Brooks)
Followup-To: comp.unix.cray
Distribution: usa
Organization: Stanford University
Lines: 16


As regards the Cray-3 GaAs devices:
I work on GaAs (ohmic contacts, MESFETs) and can speculate a little
bit about this, but I don`t know actually what Cray`s done for the GaAs
based cpu.  You are right about hole mobility in GaAs (Muller &Kamins
has 8800 cm2/Vs vs 440 for electrons vs. holes for 300degK, though this
is variable).  They say you don`t build ptype devices in GaAs so a 
CMOS like equivalent doesn`t exist---at least to my knowledge.

More likely there is a set of ntype MESFETs that have "complementary"
like threshold voltages.  When one is on, the other is off (basically
one is an enhancment mode FET and the other is a depletion mode).

It would be interesting to know exactly what Cray has done though.

Mike Brooks/Stanford Electronics Labs (solid state)/SU