Xref: utzoo comp.unix.cray:19 sci.physics:9017 comp.lsi:782
Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!wasatch!cs.utah.edu!michell
From: michell%cs.utah.edu@wasatch.utah.edu (Nick Michell)
Newsgroups: comp.unix.cray,sci.physics,comp.lsi
Subject: Re: GaAs CMOS in Cray-3 ?
Keywords: Cray-3, GaAs, LSI, CMOS, hole mobility
Message-ID: <2242@wasatch.utah.edu>
Date: 25 Jul 89 18:18:46 GMT
References: <7048@microsoft.UUCP>
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My understanding was that the Cray-3 uses Buffered FET Logic with
only depletion-mode devices.  This is fast but uses a lot of power -
no problem if you've only got a few hundred gates on a chip.
I don't remember who they're getting parts from, but I think it's
either Gigabit or Triquint.

Enhancement and Depletion-mode devices can be made using MESFETs, and
Nmos-like circuits can be built (with a lot of restrictions).  Vitesse
claims to be able to make VLSI-density chips with fairly low power
(much lower than ECL, at any rate), but the gates are not as fast as
in the parts Cray is using.

Complementary logic is possible using JFETs, but as already pointed out,
the performance of the p-type devices is pretty horrible.

/Nick Michell, University of Utah 	michell@cs.utah.edu