Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!uflorida!haven!grebyn!ckp
From: ckp@grebyn.com (Checkpoint Technologies)
Newsgroups: comp.sys.amiga
Subject: Re: Stack
Message-ID: <12238@grebyn.com>
Date: 24 Jul 89 15:12:30 GMT
References: <2105@hub.UUCP>
Reply-To: ckp@grebyn.UUCP (Checkpoint Technologies)
Organization: Grebyn Corp., Vienna, VA, USA
Lines: 23

In article <2105@hub.UUCP> dougp@voodoo.ucsb.edu writes:
>
>	Is there any particular reasor that no microprocessor has limit
>registors for the stack? What I mean by limit registers is a pair of
>registors which contains the minimum alowable stack address and the 
>maximum alowable stack address, and cause an exception, trap or
>interrupt when some code attempts to move the stack pointer out of
>the range they discribe.

	Well, the DEC KDJ11 microprocessor has a stack lower limit
register, but this is only for the kernel stack pointer. For simple
stack limit checking, you can create unaddressable pages on either end
of the stack with a decent MMU (the A2500 has just such an MMU but can't
use it this way just yet). Other than those two - I don't know of any
CPUs with hardware stack range checking, and I agree it would be a
useful item. Or else... use the new Motorola 88000 RISC architecture -
it has no built-in concept of a stack... 

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