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From: mwm@eris.berkeley.edu (Mike (I'll think of something yet) Meyer)
Newsgroups: comp.sys.amiga.tech
Subject: Re: Need information about 68010.
Keywords: 68010, 68000
Message-ID: <26461@agate.BERKELEY.EDU>
Date: 19 Jul 89 09:24:58 GMT
References: <1407@rivm05.UUCP> <116164@sun.Eng.Sun.COM> <26405@agate.BERKELEY.EDU> <116365@sun.Eng.Sun.COM>
Sender: usenet@agate.BERKELEY.EDU
Reply-To: mwm@eris.berkeley.edu (Mike (I'll think of something yet) Meyer)
Organization: Missionaria Phonibalonica
Lines: 62

In article <116365@sun.Eng.Sun.COM> raz@sun.UUCP (Steve -Raz- Berry) writes:
<In article <26405@agate.BERKELEY.EDU> mwm@eris.berkeley.edu (Mike (I'll think of something yet) Meyer) writes:
<)>In article <116164@sun.Eng.Sun.COM> raz@sun.UUCP (Steve -Raz- Berry) writes:
<)><In article <1407@rivm05.UUCP> ccemdd@rivm.UUCP (Marco Dedecker) writes:
<)<>I own an A500, and I would like to know if there is someone that has
<)<>replaced his 68000 by an 68010.
<
<)<3 line instruction cache. This allows very small loops to execute 
<)<internal to the chip. It's effect however is nearly nil except in 
<)<very rare cases.
<
<)In reality, most any simple operation on a block of memory (like copying it,
<)or searching for a value) can be written to land in that cache. This
<)means that those operations don't wait for intermediate instruction
<)fetches, and get to run at memory speed (much nicer than an unnamed
<)architechtures "block move instructions"; also more usefull).
<
<Gee, I thought that was what the blitter was for :-)

You're right, the blitter does that. On the other hand, the 68010 may
be able to do it faster. The difference will be small. Except that the
Amiga has dual-ported memory, so the CPU can be doing usefull things
while the blitter is doing the block op. On '0[123]0 systems without
dual-ported memory, a blitter is a waste as far as speed is concerned.

<Can you show me
<examples of how Lattice optimizes code for the '010? I can't think of
<hardly anything else that such a small cache could be used for besides
<block moves. What kind of tight loop uses only three words?

No, I can't show you code from Lattice, because I haven't gone looking
for it. Maybe one of the SAS or Lattice people will talk about it. I
do know that the mem* routines have been using dbcc instructions in
ways that will run in loop mode since 4.0. Currently, they get
generatted inline (who wants to waste time calling functions for
those?).

The actual criterion is a single 1-word instruction before a dbcc
instruction. Things that come to mind to fit that are: checksums. Bit
counting. long-precision arithmetic. Probably others.

Finally, Josh Rovero <PROVERO@WSMR-SIMTEL20.ARMY.MIL> reported by mail
that RAM: ran 40% faster after converting to an '010. I haven't
verified it, and I'm not going to go disassemble my machine to do so.

<)Note that the tighter specs on the '010 make the converse more likely
<)to be true. Converting to a ceramic '010 is a recommended step when
<)dealing with the "double expansion guru blues."
<
<I think you misunderstood me. I *did* blame the '010 (for being
<fried).  I would have prefered a ceramic part, but hey, it was free.
<I was just trying to impress upon the need for caution.

I didn't mistunderstand you. I just wanted to point out that things are
more likely to improve than the opposite when going to an '010.

	<mike
--
So this is where the future lies			Mike Meyer
In a beer gut belly; In an open fly			mwm@berkeley.edu
Brilcreamed, acrylic, mindless boys			ucbvax!mwm
Punching, kicking, making noise				mwm@ucbjade.BITNET