Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!tut.cis.ohio-state.edu!purdue!decwrl!hplabs!hp-pcd!hpvcfs1!johne
From: johne@hpvcfs1.HP.COM (John Eaton)
Newsgroups: comp.sys.ibm.pc
Subject: Re: Pagemode vs Cache Memory Architectures
Message-ID: <670014@hpvcfs1.HP.COM>
Date: 23 Jul 89 23:24:28 GMT
References: <1399@esunix.UUCP>
Organization: Hewlett Packard, Vancouver, WA
Lines: 14

<<<<
< 
< What I don't understand is how are the RAM's interleaved?  An example
< will help to explain my question: let's say I have a 386 with 4 Meg of
< RAM composed of 32 1Meg x 1 DRAM chips.  
----------
Will not work. Use 32 256K x 4 rams instead to give you four banks of
32 bit wide memory. The four banks are decoded off the LOWEST 32 bit
addresses so that reading consecutive 32 bit words causes acceses to
sequential banks.


John Eaton
!hpvcfs1!johne