Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!purdue!ames!uhccux!munnari.oz.au!murtoa.cs.mu.oz.au!ditmela!yarra!melba!baby!gnb From: gnb@bby.oz (Gregory N. Bond) Newsgroups: comp.arch Subject: Re: RISCs Register sets and PDP 10/20s Message-ID: Date: 28 Jul 89 05:56:22 GMT References: <550@augean.OZ> Sender: gnb@melba.bby.oz Organization: Burdett, Buckeridge and Young Ltd. Lines: 24 In article <550@augean.OZ> idall@augean.OZ (Ian Dall) writes: So why not put the "registers" in memory? If the "registers" are the [...] I suspect the problem is that there is still a significant gap between the access times of a register and of a cache location. Still, I kind of like the idea of an infinitly large demand paged register set! You aren't wrong. How many caches can do 2 reads/1 write per 50ns cycle? And how much do they cost? The other problem is instruction bits. It is easy to specify 3 addresses if each one is 5 bits wide, but much harder if they are general addresses. Yes, it would work, it would remove the nasty register selection phase of the compiler, but you can make fatser machines cheaper using registers. Greg. -- Gregory Bond, Burdett Buckeridge & Young Ltd, Melbourne, Australia Internet: gnb@melba.bby.oz.au non-MX: gnb%melba.bby.oz@uunet.uu.net Uucp: {uunet,pyramid,ubc-cs,ukc,mcvax,prlb2,nttlab...}!munnari!melba.bby.oz!gnb