Path: utzoo!utgpu!watmath!att!tut.cis.ohio-state.edu!mailrus!ames!apple!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: RISCs Register sets and PDP 10/20s
Message-ID: <43445@bbn.COM>
Date: 28 Jul 89 14:43:17 GMT
References: <550@augean.OZ>
Sender: news@bbn.COM
Reply-To: slackey@BBN.COM (Stan Lackey)
Organization: Bolt Beranek and Newman Inc., Cambridge MA
Lines: 21

In article <550@augean.OZ> idall@augean.OZ (Ian Dall) writes:
>All this talk of PDP 10s aliasing memory to the first locations of memory
>reminded me of something I was thinking about some time ago.
>So why not put the "registers" in memory? 

[Insert generic "it's been done" message here]

The TI 990/9900 did this - the CPU had a 'workspace pointer' which
pointed to R0, the base of the register file, hopefully in a section
of main memory that was implemented in Schottky RAM.  Thus, a context
switch would be a matter of loading only a few registers.  Actually,
register windowing could be simulated with this facility.

This would be tough to get performance, because you need real fast
access to the register file, preferably multi-port AND real fast
access.  Sure, the current register set could be moved in and out, but
that defeats the original purpose.

Now would 40,000 other readers mind adding more architectures to the
list?  Preferably really old ones.  :-)
-Stan