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Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.milw.wisc.edu!bbn!oliveb!tymix!epimass!jbuck
From: jbuck@epimass.EPI.COM (Joe Buck)
Newsgroups: comp.arch,comp.misc
Subject: Re: Info on DSP chips
Message-ID: <3469@epimass.EPI.COM>
Date: 31 Jul 89 17:56:02 GMT
References: <337@venus.iotek.UUCP> <23379@winchester.mips.COM> <277@melair.UUCP>
Reply-To: jbuck@epimass.EPI.COM (Joe Buck)
Followup-To: comp.arch
Organization: Entropic Processing, Inc., Cupertino, CA
Lines: 25

In article <277@melair.UUCP> low@melair.UUCP (Rick Low) writes:
>..., then I wrote a 1024-point, radix-4,
>complex, floating-point (obviously), looped (i.e. not inline coded)
>FFT for this beast. [ the TI TMS320C30 ].
>
>I simulated this FFT using TI's C30 simulator and assuming zero wait
>states for external memory.  This FFT ran in 2.71 ms for an average
>of about 17 MFLOPs.  The control structure of this FFT -- i.e. non-butterfly
>code -- took 18 percent of the total execution time.

I'm currently working on the real thing, not just the simulator.

Unless you took account of a bug in the C30 simulator, your number is
a bit too optimistic: it always takes two cycles to write to external
memory, even with zero wait states; the C30 simulator counts it as one.
To get the true time, add a cycle for each external memory write cycle.

Yes, zero wait state external RAM is buildable, especially since all the
external RAM doesn't have to have the same number of wait states.  I'm
currently writing code for a board with six C30's on it, with 8K of
0-wait-state external memory for each.  It brings one back to the old
days of computing, where you count cycles and count memory words.

-- 
-- Joe Buck	jbuck@epimass.epi.com, uunet!epimass.epi.com!jbuck