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From: verwer@ruuinf.cs.ruu.nl (Nico Verwer)
Newsgroups: comp.arch
Subject: Re: delayed branch
Summary: > 90% !
Message-ID: <1489@ruuinf.cs.ruu.nl>
Date: 1 Aug 89 16:00:13 GMT
References: <2246@taux01.UUCP>
Organization: Univ of Utrecht, Dept of CS
Lines: 22

In article <2246@taux01.UUCP>, cdddta@tasu76.UUCP (David Deitcher) writes:
> "Delayed branch" is a technique used by RISC machines to make use of the
> extra cycle needed to calculate branch targets. The compiler will put
> an instruction after the branch to be executed by the CPU while the
> branch target is being calculated. Does anyone have information as to
> how often the compiler is able to put a useful instruction after the
> branch as opposed to filling it with a NOP?
In "reduced instruction set computers", Communications of the ACM, jan. 1985,
(pp. 8 -- 21), D.A Patterson writes (on page 13):
" RISC optimizing compilers are able to succesfully rearrange instructions
" to use the cycle after the delayed branch more than 90 percent of the
" time. Hennesy has found that more than 20 percent of all instructions
" are executed in the delay after the branch.
The article he is referring to is in IEEE Trans.Comput., but had to be
published yet at that time.

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