Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!iuvax!pur-ee!hankd
From: hankd@pur-ee.UUCP (Hank Dietz)
Newsgroups: comp.arch
Subject: Re: delayed branch
Message-ID: <12479@pur-ee.UUCP>
Date: 3 Aug 89 17:58:26 GMT
References: <2246@taux01.UUCP> <1462@l.cc.purdue.edu> <26139@shemp.CS.UCLA.EDU> <1989Aug2.160111.9324@jarvis.csri.toronto.edu>
Reply-To: hankd@pur-ee.UUCP (Hank Dietz)
Organization: Purdue University Engineering Computer Network
Lines: 12

In article <1989Aug2.160111.9324@jarvis.csri.toronto.edu> glenn@csri.toronto.edu (Glenn Mackintosh) writes:
>... For example the compiler could
>change this to do a compare against 4 and move the increment into the delay
>slot after the test. ...

I haven't seen loop transforms done to optimize FINE GRAIN pipelines...
although it shouldn't be all that hard to do.  A few years ago, somebody (at
Stanford?) had a paper out on converting between equality and inequality
comparisons so that better instruction sequences would apply.  That's the
closest I recall seeing.

						-hankd@ecn.purdue.edu