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From: roelof@idca.tds.PHILIPS.nl (R. Vuurboom)
Newsgroups: comp.arch
Subject: Re: delayed branch
Message-ID: <221@ssp1.idca.tds.philips.nl>
Date: 3 Aug 89 16:16:43 GMT
References: <2246@taux01.UUCP> <1996@se-sd.NCR.COM>
Organization: Philips Telecommunication and Data Systems, The Netherlands
Lines: 19

In article <1996@se-sd.NCR.COM> lord@se-sd.UUCP (Dave Lord (SSP)) writes:
>Hopefully this will change. Anyone have
>any idea what percentage of typical code is branches? It would be
>interesting to know how much performance could be gained 
>by filling those slots.

For the motorola 68k I've seen one study quoting 23% of executed code 
being branches. I seem to remember hearing somewhere else a figure of
1 in 6 so somewhere between 1 in 4 and 1 in 6 would be my guess.

Which explains why (to answer an unasked question :-) you'll see instruction
cache line sizes for 68k architectures getting up to 16 bytes but no more: 
average instruction length is 3 bytes  3x5=15 pulling in extra instructions 
would just waste memory bandwidth.
-- 
I don't know what the question means, but the answer is yes...
KLM - Koninklijke Luchtvaart Maatschappij => coneenclicker lughtfart matscarpie
Roelof Vuurboom  SSP/V3   Philips TDS Apeldoorn, The Netherlands   +31 55 432226
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