Path: utzoo!utgpu!jarvis.csri.toronto.edu!rutgers!usc!apple!apple.com!pauls
From: pauls@apple.com (Paul Sweazey)
Newsgroups: comp.arch
Subject: Re: delayed branch
Message-ID: <3343@internal.Apple.COM>
Date: 3 Aug 89 22:43:44 GMT
Sender: usenet@Apple.COM
Organization: Apple Computer, Inc.
Lines: 17
References:<2246@taux01.UUCP> <1996@se-sd.NCR.COM> <221@ssp1.idca.tds.philips.nl>

In article <221@ssp1.idca.tds.philips.nl> roelof@idca.tds.PHILIPS.nl (R. 
Vuurboom) writes:
> For the motorola 68k I've seen one study quoting 23% of executed code 
> being branches. I seem to remember hearing somewhere else a figure of
> 1 in 6 so somewhere between 1 in 4 and 1 in 6 would be my guess.
> 
> Which explains why (to answer an unasked question :-) you'll see instruction
> cache line sizes for 68k architectures getting up to 16 bytes but no more: 
> average instruction length is 3 bytes  3x5=15 pulling in extra instructions 
> would just waste memory bandwidth.

However, there is a high probability that the branch is a few instructions away, or will soon run or branch to the remainder of the larger cache line.  Other issues such as memory operation or interconnect bandwidth and latency may be the real deciding factors.

Paul Sweazey
Apple Computer, Inc.
pauls@apple.com
(408)-974-0253