Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!apple!sun-barr!cs.utexas.edu!uunet!ficc!peter
From: peter@ficc.uu.net (Peter da Silva)
Newsgroups: comp.arch
Subject: Re: RISCs Register sets and PDP 10/20s
Message-ID: <5504@ficc.uu.net>
Date: 3 Aug 89 20:46:28 GMT
References: <550@augean.OZ> <43445@bbn.COM> <3301@alliant.Alliant.COM>
Organization: Xenix Support, FICC
Lines: 73

In article <3301@alliant.Alliant.COM>, werme@Alliant.COM (Ric Werme) writes:
> In article <43445@bbn.COM> slackey@BBN.COM (Stan Lackey) writes:
> >Now would 40,000 other readers mind adding more architectures to the
> >list?  Preferably really old ones.  :-)

The 1802 has 16 16-bit registers, one 8-bit register, and two 4-bit
registers. The 4-bit registers (P and X) point to the registers that
will be used as PC and SP. The 8-bit register is the accumulator. All
memory reads and writes go via the AC, so loading a register takes 4
instructions:

	Load value
	PLO reg	(Put LOw byte)
	Load value
	PHI reg (Put HIgh byte)

The subroutine call involved changing the P register to a new register
with the new PC in it, and changing back to the old register to return.
To save space a standard call and return technique was set up:

Five register are set aside:

	PC	Program Counter
	SP	Stack Pointer
	LINK	Holds top word of stack.
	CALL	Holds call-routine address. Starts at CALLP
	RET	Halds return-routine address. Starts at RETP

Then you have the following code:

CALLP:	GLO	LINK
	STXD		Store via X and Decrement (push)
	GHI	LINK
	STXD
	GLO	PC
	PLO	LINK
	GHI	PC
	PHI	LINK	Now the old LINK is pushed, new LINK is old PC
	LDA	LINK
	PLO	PC
	LDA	LINK
	PHI	PC
	SEP	PC	Set Program counter to be PC
	BR	CALLP	Go back and do it again.
RETP:	GLO	LINK
	PLO	PC
	GHI	LINK
	PHI	PC
	INR	SP
	LDXA		Load via X and increment (pop)
	PHI	PC
	LDX
	PLO	PC
	SEP	PC
	BR	RETP

Now you could make a subroutine call:

	SEP	CALL
	DATA	SUBR	Address of subroutine, inline after instruction.

> An architectural issue - the Z8 convinced me that one of the key criteria
> in choosing a processor (or designing one) is how general purpose the
> general purpose registers are.

1802 registers were quite general purpose :->, but the Forth inner
interpreter loop was *faster* than a normal subroutine call! It would
have helped if LDXA was LDAX instead...
-- 
Peter da Silva, Xenix Support, Ferranti International Controls Corporation.
Business: peter@ficc.uu.net, +1 713 274 5180. | "The sentence I am now
Personal: peter@sugar.hackercorp.com.   `-_-' |  writing is the sentence
Quote: Have you hugged your wolf today?  'U`  |  you are now reading"