Path: utzoo!censor!geac!jtsv16!uunet!ginosko!rex!ukma!rutgers!mit-eddie!uw-beaver!blake!Tomobiki-Cho!mrc
From: mrc@Tomobiki-Cho.CAC.Washington.EDU (Mark Crispin)
Newsgroups: comp.arch
Subject: Re: Flash! 16 not power of 2! [really, CISC-to-the-max]
Message-ID: <3145@blake.acs.washington.edu>
Date: 8 Aug 89 00:15:17 GMT
References: <38139@stellar.UUCP> <24889@winchester.mips.COM>
Distribution: usa
Organization: Mendou Zaibatsu, Tomobiki-Cho, Butsumetsu-Shi
Lines: 65

In article <24889@winchester.mips.COM> mash@mips.COM (John Mashey) writes:
>In fact, this leads to an interesting question for the old-timers:
>how about more reminiscing of instruction-set-architecture features of the
>machines designed in the 50s and 60s, that have essentially
>disapeared in those designed in the 70s and 80s...?

I don't know if any of this has been mentioned yet:

The PDP-8 only had 8 machine instructions, but oh that 8th instruction!
Opcode 7 was OPR, which interpreted the following 9 bits as various
miscellaneous non-memory referencing operations.  A couple of the bits
identified a particular "group" of instructions (= the interpretation of
the other bits).  You could "microprogram" instructions of the same group
together so they all got executed at the same time, with amazing and useful
results.

The PDP-10 didn't have condition codes, but it did have a test instruction,
which had 64 opcodes, depending upon what you tested (right half from
immediate, left half from immediate, register from memory, register from
memory swapped), what you did with the test bits (no modification, set to
zeros, set to ones, complement), and under what conditions you would skip
the next instruction (never, always, if all masked bits zero, if any masked
bit one).  This (along with the other skip instructions) let you create
elaborate if chains that were far more elaborate than was possible with the
if/else of high level languages.  One cute trick was:
	TRCE AC,B1+B2
	TRCE AC,B1+B2
	TRCE AC,B1+B2
where B1 and B2 are two separate single right half bits.  TRCE is Test
Right half from immediate, Complement the masked bits when done, and skip
if any masked bits were Equal to zero.  This would swap the state of the
two bits.  The third instruction could have been TRC (never skip) but it
can never skip (figure it out for yourself) and it's easier to remember
as three TRCE's.  I used to call this the "tricky-tricky trick" based on
the hacker pronounciation of those opcodes.

The PDP-10 had every form of bitwise logic instruction, including those
instructions that were normally not useful.  One such instruction was the
equivalence instruction, which compared two values and returned 1 for each
bit in the two values which was equal.  In other words, equivalence was the
opposite of exclusive-OR.  One very common type of register index value was
the AOBJN-pointer, which had a negative count in the left half and an index
in the right half.  The AOBJN (Add One to Both Halves and Jump if Negative)
instruction would go at the tail of a loop and would cause an interation
until the count ran out.  Now, if you had a *positive* count in a register
(say T1) and needed to set up an AOBJN pointer in T1 with a non-zero
initial index (say FOO), you would need something like:
	MOVN T1,T1		; negate T1 (or MOVNS T1)
	HRL T1,T1		; copy right half to left (or HRLS T1)
	HRRI T1,FOO
but with equivalence, you could do:
	HRLOI T1,-1(T1)		; put C(T1)-1 into left half, -1 in right half
	EQVI T1,FOO		; equivalence with 0,,FOO
The first instruction combines a subtract of 1, load into left half, and set
to ones of the right half.  Since the left half of an immediate is 0, the
equivalence does a one's-complement of the left half (which is a two's-
complement of the original value due to the subtract of 1) and a copy of the
right half.

Mark Crispin / 6158 Lariat Loop NE / Bainbridge Island, WA 98110-2020
mrc@CAC.Washington.EDU / MRC@WSMR-SIMTEL20.Army.Mil / (206) 842-2385
Atheist & Proud / 450cc Rebel pilot -- a step up from 250cc's!!!
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