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From: tim@crackle.amd.com (Tim Olson)
Newsgroups: comp.lang.c
Subject: Re: IEEE floating point format
Message-ID: <26532@amdcad.AMD.COM>
Date: 29 Jul 89 21:20:09 GMT
References: <2170002@hpldsla.HP.COM> <9697@alice.UUCP> <1270@atanasoff.cs.iastate.edu>
Sender: news@amdcad.AMD.COM
Reply-To: tim@amd.com (Tim Olson)
Organization: Advanced Micro Devices, Inc. Sunnyvale CA
Lines: 26

In article <1270@atanasoff.cs.iastate.edu> hascall@atanasoff.cs.iastate.edu.UUCP (John Hascall) writes:
| In article <9697@alice.UUCP> ark@alice.UUCP (Andrew Koenig) writes:
| >In article <2170002@hpldsla.HP.COM>, manoj@hpldsla.HP.COM (Manoj Joshi) writes:
|  
| >> What is the format for the IEEE floating point storage
|  
| >The format is:
|  
| >	field		32-bit format		64-bit format
|  
| >	sign			1			1
| >	exponent		8			12
| >	fraction		23			55
|                             ------                    -----
| 				32 (ok!)                68 (huh?)
|  
|       Is it <1,8,55>, <1,12,51> or some other thing?
|       (or have they found a way for more hidden bits :-)

Neither.  Double precision fields are 1 sign, 11 exponent, and 52
fraction bits.


	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)