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From: u91@nikhefh.hep.nl (Simon Goble)
Newsgroups: comp.lsi.cad
Subject: Request for info on 'Espresso'
Keywords: Espresso, ABEL, Logic Reduction
Message-ID: <231@nikhefh.hep.nl>
Date: 2 Aug 89 14:20:40 GMT
Organization: Nikhef-H, Amsterdam (the Netherlands).
Lines: 25




  Does anyone have any info on the logic reduction program
'Espresso #2.2' from UC Berkeley?

  We have just got around to installing ABEL_3.1 and while
investigating the REDUCE program with the Espresso option
(it complains that it can't find it -anywhere!) have been
experimenting with Espresso on its own.

  The reason for the interest is that I would like to use
ABEL to describe our state machines and then use its output
to generate a low level gate description for a gate array.

  What would be really useful is something that would take the
sums of product terms and turn them into 2->4 input NAND/NOR
logic.

u91@nikhefh.hep.nl (Simon Goble)
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