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From: kdg@nirvo.uucp (Kurt Gollhardt)
Newsgroups: comp.unix.i386,comp.sys.att
Subject: Re: Cache disabling -- why a big deal?
Summary: 82385 has "don't cache" input pin
Keywords: cache 80386 dual ported RAM
Message-ID: <24CE8F41.1FB0@nirvo.uucp>
Date: 27 Jul 89 04:27:44 GMT
References: <40@oink.UUCP> <7831@hoptoad.uucp> <2944@cuuxb.ATT.COM>
Reply-To: kdg@nirvo.UUCP (Kurt Gollhardt)
Distribution: na
Organization: Nirvonics Inc., Plainfield, NJ
Lines: 13

In article <2944@cuuxb.ATT.COM> fmcgee@cuuxb.UUCP (Frank W. McGee) writes:
>I'm not an expert on the 82385, but I believe that it may be the case
>that it doesn't know that some areas of memory shouldn't be cached.

The 82385 has a (single) input pin which says "don't cache this address".
It is up to external circuitry - read: motherboard designer - to decode
the addresses which are not to be cached.  Unfortunately, this is not
usually done in a flexible way.
-- 
  ==============                                          ==============
  #  Kurt Gollhardt                 Nirvonics, Inc. -- Plainfield, NJ  #
  #  ...!rutgers!nirvo!kdg            Software Design and Consulting   #
  ==============                                          ==============