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From: jmm@ecijmm.UUCP (John Macdonald)
Newsgroups: comp.unix.wizards
Subject: Re: Information on SPARC assembly (atomic Test and Set)
Message-ID: <281@ecijmm.UUCP>
Date: 22 Jul 89 15:22:09 GMT
References: <350@osc.COM> <577@lakart.UUCP>
Reply-To: jmm@ecijmm.UUCP (John Macdonald)
Organization: R. H. Lathwell Associates, Elegant Communications, Inc.
Lines: 48

In article <577@lakart.UUCP> dg@lakart.UUCP (David Goodenough) writes:
> [quoted material deleted]
>
>I have never understood the need for a test and set instruction, when
>you can make do with adc (add with carry). Allow me to explain:
>
>The point behind TAS is to allow a process to test if a flag is set or
>clear, and set it no matter what the result. But why does the test have
>to be in the same instruction? In fact all that is needed is the ability
>to capture the state of a bit, setting it as you do the capture, and
>test it later. If you think about the following:
>
>	[example of multitasking use of ADC deleted]
>
>Note that Task 1 got interrupted between sampling the bit, and testing it,
>_BUT_IT_DIDN'T_MAKE_ANY_DIFFERENCE_ - the system still worked.
>
>So the bottom line is all you need is the ability to capture the state
>of a bit, and set it no matter what, all in one atomic instruction.

This is true for a single-processor multi-tasking situation.  There is a
stronger requirement for a multi-processor shared memory situation.  In
that case, there must be provision for the atomic instruction to:

1. Read and check the status of the old value.
2. Change to a (possibly) new value.
3. Write back the new value.

(the same as described above, plus:)

4. Ensure that no other processor can access the old value between
    steps 1 and 3!

In many processors, most read-modify-write instructions release their
access path to the memory during step 2 and then regain it for step 3.
This allows another processor to use the memory path without waiting.
In such processors, there is generally a small number of instructions
which are guaranteed to not release the memory path.  For example, on
the Motorola 68020, the TAS (test and set), CAS (compare and swap),
and CAS2 (compare and swap twice) instructions all lock the memory
bus for the duration of all of their accesses; while other instructions
(e.g. add immediate to memory) which have a read-modify-write pattern
do not.  This type of design trades off increased speed for the non-
locking operations against the reuirement that the programmer use one
of the locking instructions whenever there may be a multi-processor
simultaneous access to the datum.
-- 
John Macdonald