Path: utzoo!utgpu!watmath!att!dptg!rutgers!mcnc!rti!sunpix!matthew
From: matthew@sunpix.UUCP ( Sun Visualization Products)
Newsgroups: sci.electronics
Subject: Re: 6551 ACIA questoin.
Message-ID: <743@greens.UUCP>
Date: 7 Aug 89 15:33:49 GMT
References: <2528@tymix.UUCP>
Organization: Sun Microsystems, Research Triangle Park, NC
Lines: 36


 In request for more info on the 6551 ACIA command register, Heres some 
info from data sheets on the 6551.

Command Register:
	Bit 7 6 5  [Parity Control]
	    - - 0  Parity disabled - No parity bit generated. None received.
	    0 0 1  Odd parity received and transmitted
	    0 1 1  Even parity received and transmitted
	    1 0 1  Mark parity sent, receive parity check disabled
	    1 1 1  Space parity sent, receive parity check disabled

	Bit 4      [Echo Control]
	    0      Normal
	    1      Echo (bits 2 and 3 must be zero)

	Bit 3 2    [Transmitter Control]
	    0 0    Transmit Interupt disabled. RTS* = High, Transmitter = off
	    0 1    Transmit Interupt enabled.  RTS* = Low,  Transmitter = on
	    1 0    Transmit Interupt disabled. RTS* = Low,  Transmitter = on
	    1 1    Transmit Interupt enabled.  RTS* = Low,  Transmitter = BREAK

	Bit 1      [IRQ Control]
	    0      IRQ* interrupt enabled from bit 3 of status word.
	    1      IRQ* interrupt disabled.

	Bit 0      [DTR Control]
	    0      Disable receiver and all interrupts. (DTR* high)
	    1      Enable receiver and all interrupts. (DTR* low)


-- 
Matthew Lee Stier                            |
Sun Microsystems ---  RTP, NC  27709-3447    |     "Wisconsin   Escapee"
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