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From: rcpieter@eutrc4.urc.tue.nl (Pieter Schoenmakers)
Newsgroups: comp.arch
Subject: Re: delayed branch
Message-ID: <828@eutrc3.urc.tue.nl>
Date: 8 Aug 89 18:11:17 GMT
Sender: news@eutrc3.urc.tue.nl
Reply-To: rcpieter@rc4.urc.tue.nl
Organization: Eindhoven University of Technology, The Netherlands
Lines: 10

Just wondering---
 - What happens on existing processors which use delayed branches when the
instruction put in the branch instruction's shadow is also a branch?
 - Do existing processors have a seperate adder for use by branches only, or
are there restrictions on the possible instructions which can be put in the
shadow?
 - Are there any processors which use branch delaying and don't have a
seperate address calculation adder?

Tiggr