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From: seanf@sco.COM (Sean Fagan)
Newsgroups: comp.arch
Subject: Re: What is a Mainframe?
Message-ID: <2968@scolex.sco.COM>
Date: 8 Aug 89 00:37:35 GMT
References: <125@ssp1.idca.tds.philips.nl> <20752@winchester.mips.COM> <27637@lll-winken.LLNL.GOV> <164@bms-at.UUCP>
Reply-To: seanf@scolex.UUCP (Sean Fagan)
Distribution: comp.arch
Organization: The Santa Cruz Operation, Inc.
Lines: 42

In article <164@bms-at.UUCP> stuart@bms-at.UUCP (Stuart Gathman) writes:
>In article <27637@lll-winken.LLNL.GOV>, brooks@maddog.llnl.gov (Eugene Brooks) writes:
>> In article <33942@bu-cs.BU.EDU> bzs@bu-cs.BU.EDU (Barry Shein) writes:
>
>Most of the massive I/O bandwidth on mainframes is wasted due  to
>stupid  software.   They can copy files at 3 Mbytes/sec, but even
>with only one user, editing is faster on a PC. 

*sigh*  *Completely* different thoughts, here.  FSE, under NOS on a Cyber,
was quite fast, for what it was used for, and for what it did.  It had the
advantage of being a full-screen editor without needing to respond to each
and every keypress.  Helped system load a *lot*.

>I think that even in I/O bandwidth,  traditional  (three  letter)
>mainframes  are about to be overtaken.  A typical system has 12 x
>3 Mbyte/sec independent (and intelligent) channels.   This  gives
>an   aggregate  throughput  of  288  Mbits/sec.   The  peripheral
>controller  Intel  offers  with  the  486  claims  an   aggregate
>throughput of 150 Mbits/sec with 8 independent channels.  This is
>getting close, and it is certainly not hard to beat a 6 Mips  CPU
>these  days.   I  hear  that  the  NeXT  has  a  high  throughput
>peripheral chip also.

You're forgetting something:  multi-ported memory.  Let's take my
favorite machine, a CDC Cyber.  Let's take one that is maxed out on
processing power, with 2 CP's and 20 IO processors (each set of 10
PP's shares one ALU).  The memory is organized into 8 banks, and
would have, I believe, a 50 ns access time (i.e., accessing any
random memory location will take at most 50 ns), and a 25 ns cycle
time on the CP.  However:  the memory is quad-ported.  Each of the
CPs, and each of the PP's ALUs, can access memory simeultaneously (sp?).
I have not seen *any* micro that can do that, even for 2 channels (cpu
and dma), and this slows things down quite a bit.

I think it was Henry Spencer who claimed that a bitblt coprocessor was a
waste unless you had free cycles on your processor.  Cyber's don't need
that, and most other mainframes don't, either.

-- 
Sean Eric Fagan  |    "Uhm, excuse me..."
seanf@sco.UUCP   |      -- James T. Kirk (William Shatner), ST V: TFF
(408) 458-1422   | Any opinions expressed are my own, not my employers'.