Path: utzoo!utgpu!watmath!att!tut.cis.ohio-state.edu!gem.mps.ohio-state.edu!ginosko!uunet!crdgw1!sungod!davidsen From: davidsen@sungod.crd.ge.com (ody) Newsgroups: comp.arch Subject: Re: hardware complex arithmetic support Message-ID: <1672@crdgw1.crd.ge.com> Date: 15 Aug 89 12:09:16 GMT References: Sender: news@crdgw1.crd.ge.com Reply-To: davidsen@crdos1.UUCP (bill davidsen) Organization: General Electric Corp. R&D, Schenectady, NY Lines: 24 In article jk3k+@andrew.cmu.edu (Joe Keane) writes: | Are there any architectures that have hardware support for complex arithmetic? | For example, dividing two complex numbers (in rectangular form) takes 6 | multiplications, 2 divisions, and 3 add/subtracts, if i count correctly. With | appropriate functional units that can be hooked up in the right way, this could | be done in a couple of clock cycles. Actually I didn't write the pseudo-microcode, but I *think* the minimum time is the sum of mpy,div,add for the longest path. And none of those happen in a few cycles unless you pipeline. Now, assuming that you did build a machine which had the right hardware, if you have a vector long enoung you can do anything on just ove one clock cycle. Why hasn't anyone built a complex FPU? This seems like a reasonable thing to do, in term of being common. It could probably be built into one of the existing micro FPUs without too much trouble (obviously needs more microcode), but I doubt that you win much because the chip doesn't have the power to do a lot in parallel. bill davidsen (davidsen@crdos1.crd.GE.COM) {uunet | philabs}!crdgw1!crdos1!davidsen "Stupidity, like virtue, is its own reward" -me