Path: utzoo!utgpu!watmath!att!tut.cis.ohio-state.edu!ucbvax!hplabs!hpda!hpcupt1!hpsal2!hull From: hull@hpsal2.HP.COM (James Hull) Newsgroups: comp.arch Subject: Re: Lights (was: Perf & Diag / Cycle Counter) Message-ID: <2280008@hpsal2.HP.COM> Date: 14 Aug 89 17:39:50 GMT References: Organization: HP System Architecture Lab, Cupertino Lines: 21 > I know something like this exists on the Cray X-MP; do other machines > have cycle counters as well? The HP Precision architecture defines a control register called the Interval Timer for this purpose. Here's the relevant section of the manual: Interval Timer The Interval Timer (CR 16) consists of two internal registers. One of the internal registers is continually counting up by 1 at a rate which is model-dependent and between twice the "peak instruction rate" and half the "peak instruction rate". Reading the Interval Timer returns the value of this internal register. The other internal register contains a comparison value and is set by writing to the Interval Timer. When the counter register and the comparison register contain identical values, bit 0 of the External Interrupt Request Register is set to 1. This causes an external interrupt, if enabled. The Interval Timer can only be written by code running at the most privileged level. If the PSW S-bit is 1, the Interval Timer can only be read by code running at the most privileged level; otherwise, it can be read by code running at any privilege level.