Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!iuvax!purdue!haven!uvaarpa!babbage!mac3n
From: mac3n@babbage.acc.virginia.edu (Alex Colvin)
Newsgroups: comp.arch
Subject: [really, CISC-to-the-max]
Summary: execute register (pair); voyager spacecraft
Message-ID: <846@babbage.acc.virginia.edu>
Date: 15 Aug 89 19:32:13 GMT
References: <38139@stellar.UUCP> <24889@winchester.mips.COM>
Distribution: usa
Organization: University of Virginia
Lines: 35

In article <24889@winchester.mips.COM>, mash@mips.COM (John Mashey) writes:
> In fact, this leads to an interesting question for the old-timers:
> how about more reminiscing of instruction-set-architecture features of the
> machines designed in the 50s and 60s, that have essentially
> disapeared in those designed in the 70s and 80s...?

As Dave Wright noted (yes, Dave, I'm still a grad student) the XED
instruction isn't to be found much anymore.  It turns out to be
particularly useful in the absence of a hardware stack for pushing state.

The GE635 just XED'd the interrupt vector.  The XED'd instructions were
responsible for saving whatever state, wherever they wanted.  Voila,
programmer implemented stacks, queues, whatever.

XED was kind of an artifact of the doubleword instruction fetch of the 635.
This became difficult as they went to pipelines and variable-length
instructions.  I see that fixed-width, register-sized instructions are
coming back in fashion.

Other than that, execute instructions are handy to execute data without
messing with page control bits, etc.  Nice for interpreters, particularly
threaded.  Should also work for register pairs.  Write your own macro-
sequencer?  I've heard of a PDP-8 instruction emulator that simply did a
XEC through a table, like a fast switch statement without all the break
statements.

To tie into another thread of discussion, branches in the branch delay slot
of some RISCs appear to work like XECs, fetching one remote instruction
before restoring the PC.

To start another thread, rumor had it that one of the voyager spacecraft
uses an execute-like instruction that swaps the acumulator and the
instruction fetch register.  This can also be used to generate constants.
I read that the spacecraft approaching neptune has 32K RAM.  Surely this is
an interesting long-lived architecture.  Anyone know what it looks like?