Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.csd.uwm.edu!cs.utexas.edu!uunet!microsoft!gideony
From: gideony@microsoft.UUCP (Gideon Yuvall)
Newsgroups: comp.arch
Subject: Context-switch times
Message-ID: <7408@microsoft.UUCP>
Date: 16 Aug 89 23:02:16 GMT
Reply-To: gideony@microsoft.UUCP (Gideon Yuvall)
Organization: Microsoft Corp., Redmond WA
Lines: 8

What is a realistic context-switch penalty for the MIPS, SPARC,
88K, i860 (...) RISC chips? I'm looking for the number of cycles
needed to do the task-switch, PLUS the penalty due to the new starting
starting out with an "empty" cache.

Thanks
-- 
Gideon Yuval, gideony@microsof.UUCP, 206-882-8080 (fax:206-883-8101;TWX:160520)