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From: grosen@amadeus.ucsb.edu (Mark D. Grosen)
Newsgroups: comp.arch
Subject: Re: New TI DSP chip
Message-ID: <2224@hub.UUCP>
Date: 17 Aug 89 20:37:15 GMT
References: <2380@taux01.UUCP> <3533@epimass.EPI.COM>
Sender: news@hub.UUCP
Reply-To: grosen@amadeus.UUCP (Mark D. Grosen)
Organization: University of California, Santa Barbara
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There is a new TMS320C50 chip (as well as the TMS320C30), which was
announced at the International Conference on Acoustics, Speech, and Signal
Processing (ICASSP) in May.  This is a continuation of the fixed-point
generation.  It is basically a souped up TMS320C25, but with some neat
new features.

From the TI TMS320C25 DSP Preview Bulletin:

	*  35 and 50 ns single-cycle time
	* single cycle mult-and-add
	* zero-overhead loops
	* zero-overhead context switches (dual register set)

	* 8K (16 bit) program/data RAM
	* 544 dual-access data RAM
	* 2K boot ROM
	* on chip serial port and timer
	* software wait state generators
	* provisions for adding custom peripherals to the internal bus

	* IEEE JTAG test bus on chip


Mark D. Grosen		ARPA: grosen@amadeus.ucsb.edu
Signal Processing Lab / Communications Research Lab
ECE Dept.
University of California
Santa Barbara, CA  93106