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From: gsg0384@uxa.cso.uiuc.edu
Newsgroups: comp.arch
Subject: Vectorizing division in a do loop
Message-ID: <112400003@uxa.cso.uiuc.edu>
Date: 17 Aug 89 02:38:00 GMT
Lines: 20
Nf-ID: #N:uxa.cso.uiuc.edu:112400003:000:698
Nf-From: uxa.cso.uiuc.edu!gsg0384    Aug 16 21:38:00 1989



Hi,

I've heard that vector machines are more expensive than multi-cpu parallel
machines.  I've got two questions about vector machines.

1.  For compiler design, I think vector machine architecture is easier.
    Is this true?

2. Our machine is Ardent Titan.  Each cpu has 64-register length vector
   registers.  The problem is that this machine does not vectorize do loops
   with division.  How much harder is to implement division than the other
   three operations, + - x?  Is this a hardware limitation?

I'd rather have a vector machine than a multi-cpu parallel machine for 
my application.  I just want more people in computer industries to pay
more attention to vector machines.

Hugh