Path: utzoo!attcan!uunet!ginosko!rex!ames!ucsd!rutgers!phri!roy
From: roy@phri.UUCP (Roy Smith)
Newsgroups: comp.arch
Subject: Re: cache speed
Message-ID: <3941@phri.UUCP>
Date: 17 Aug 89 23:16:13 GMT
References: <1473@unocss.UUCP>
Reply-To: roy@phri.UUCP (Roy Smith)
Organization: Public Health Research Inst. (NY, NY)
Lines: 12

In article <1473@unocss.UUCP> mlewis@unocss.UUCP (Marcus S. Lewis) writes:
> A co-worker is building a "no compromise" performance-oriented '386
> MSDOS machine. [...] How fast do the cache chips have to be on a 33MHz 386?

	Cache is, by definition, a compromise.  If you really want to build
a "no compromise" machine, make the entire main memory out of SRAM fast
enough to keep up with the CPU.
-- 
Roy Smith, Public Health Research Institute
455 First Avenue, New York, NY 10016
{att,philabs,cmcl2,rutgers,hombre}!phri!roy -or- roy@alanine.phri.nyu.edu
"The connector is the network"