Path: utzoo!attcan!uunet!crdgw1!CRD.GE.COM
From: oconnordm@CRD.GE.COM (Dennis M. O'Connor)
Newsgroups: comp.arch
Subject: Re: cache speed
Message-ID: <1736@crdgw1.crd.ge.com>
Date: 18 Aug 89 04:23:41 GMT
References: <1473@unocss.UUCP> <3941@phri.UUCP>
Sender: news@crdgw1.crd.ge.com
Reply-To: oconnordm@CRD.GE.COM (Dennis M. O'Connor)
Organization: GE Corporate R&D Center
Lines: 35
In-reply-to: roy@phri.UUCP (Roy Smith)

roy@phri (Roy Smith) writes:
] Cache is, by definition, a compromise.  If you really want to build
]a "no compromise" machine, make the entire main memory out of SRAM fast
]enough to keep up with the CPU.

Sorry, not true. In a large memory system, propogation delays, buffer
latencies and the like will rapidly become the single largest component
in your memory latency. Buffers add delay, more chips on one line
adds capacitance, and eventually just the 1 nanosecond per foot
speed-of-light delay becomes a factor.

Once you starting adding off-chip, off-board, down-the-bus,
onto-the-board, onto-the-cRAM-chip, off-the-RAM-chip, off-board,
up-the-bus, onto-the-board and back-onto-the-chip delays,
you begin to really want on-chip cache. Lacking that,
even on-same-board cache looks good. And even lacking that,
on-only-a-few-boards cache looks better than in-only-a-few-cabinets
large RAM systems.

Cache can give you higher performance than the single-level
memory system, by using the probability that your programs
really not using ALL that memory. Smaller amounts of RAM,
due to the laws of physics, are faster than large amounts,
all other things being equal.

Summary : it's currently impossible to build a 16-megabyte NMOS,
CMOS, or TTL memory system with a 25ns access time. But with a good
cache design, you can build a system with almost the same performance.



--
 Dennis O'Connor      OCONNORDM@CRD.GE.COM       UUNET!CRD.GE.COM!OCONNORDM
	 "Did you exchange
	  a walk-om part in the war,