Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.csd.uwm.edu!cs.utexas.edu!uunet!mcvax!sunic!dkuug!freja!njk From: njk@freja.diku.dk (Niels J|rgen Kruse) Newsgroups: comp.arch Subject: Re: hardware complex arithmetic support Message-ID: <4781@freja.diku.dk> Date: 18 Aug 89 10:07:04 GMT References: <1672@crdgw1.crd.ge.com> Organization: DIKU, U of Copenhagen, DK Lines: 52 davidsen@sungod.crd.ge.com (ody) writes: > Why hasn't anyone built a complex FPU? This seems like a reasonable >thing to do, in term of being common. It could probably be built into >one of the existing micro FPUs without too much trouble (obviously needs >more microcode), but I doubt that you win much because the chip doesn't >have the power to do a lot in parallel. As far as i can tell, the main advantage of hardware support for complex arithmetic is the greater encoding density allowed by a dedicated storage format for complex numbers. Consider that it is meaningless from a numerical viewpoint to represent one component of a complex number with greater accuracy than the other. This means that a dedicated storage format need only have *one* exponent. Comparing such a double precision format to a conventional representation as 2 double precision ieee numbers, 11 exponent bits are saved and 2 hidden fraction bits are lost (because only one fraction will be normalized in general and it may be any of them). This leaves 9 extra bits which can be used to extend the range and precision, for instance 4 extra bits in each fraction and 1 extra exponent bit. This translates to more than a full decimal digit of extra precision and larger range too. The hardware cost of support for such a storage format need not be excessive, when speed is not the main concern. A low cost implementation could get away with only 2 extra instructions for each complex format (single, double precision) : a load instruction that would load the components of a complex number into 2 regular fp registers and the reverse store instruction. Complex arithmetic would then be done with a sequence of the regular instructions. The main cost of this is making registers and arithmetic units wider to accomodate the extra precision of the complex format. However, a few bits of extra precision on in-register arithmetic is useful for plain fp arithmetic too, especially for authors of math libraries. On some micro FPUs, the cost of (much) wider registers and arithmetic units have already been paid, so i really don't see a good reason why they don't support complex numbers. Didn't they think of it? It seems an obvious thing to do. Perhaps someone out there could enlighten us. -- Niels J|rgen Kruse Email njk@diku.dk Mail Tustrupvej 7, 2 tv, 2720 Vanlose, Denmark