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From: butcher@g.gp.cs.cmu.edu (Lawrence Butcher)
Newsgroups: comp.arch
Subject: SCSI on steroids, mainframes move over
Message-ID: <5932@pt.cs.cmu.edu>
Date: 22 Aug 89 06:40:56 GMT
Organization: Carnegie-Mellon University, CS/RI
Lines: 25

Recently there has been a discussion about what separates mainframes from
ordinary computers.  It isn't cycles and it isn't memory.  Generally it
seems that mainframes have huge I/O capacity, and also memory bandwidth to
support lots of concurrent activity.  Non-mainframes are weak in I/O.

Some microprocessor peripheral chips are very fancy.  Ethernet, token ring,
and some other communications chips are complete DMA systems, able to run
for quite a while without CPU intervention.  I always wanted to ask this
newsgroup why SCSI support chips look like a simple uart.  Boring.

NCR seems to have made a chip which responds to both points above.  There is
an article in Aug 10 89 Electronic Design describing the NCR53C700 SCSI
chip.  The chip includes a complete 32 bit DMA controller (capable of burst
transfers to 50 mByte/s), and some sort of programmable processor on chip.

This chip seems quite fierce.  Big time I/O seems simple and cheap.  A fast
RISC with 8 of these should be able to keep many disks busy.  Check it out.

The biggest, fastest business computers seem to run 1960's operating systems
without protection, and allow user programs to do I/O without OS assistance.
My new question.  Is fast I/O all that micros need to bury mainframes?  Or
is user level I/O needed?  If needed, how can simple hardware be built which
allows direct user level DMA I/O?

				Lawrence