Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.csd.uwm.edu!cs.utexas.edu!tut.cis.ohio-state.edu!pt.cs.cmu.edu!MATHOM.GANDALF.CS.CMU.EDU!lindsay
From: lindsay@MATHOM.GANDALF.CS.CMU.EDU (Donald Lindsay)
Newsgroups: comp.arch
Subject: Observability (was Claimed bug in 80286)
Message-ID: <5944@pt.cs.cmu.edu>
Date: 23 Aug 89 01:54:05 GMT
References: <1989Aug13.023601.594@utzoo.uucp> <310@hitech.ht.oz> <21352@cup.portal.com> <1877@brwa.inmos.co.uk>
Organization: Carnegie-Mellon University, CS/RI
Lines: 25

In article <1877@brwa.inmos.co.uk> davidb@inmos.co.uk (David Boreham) writes:
>In article <21352@cup.portal.com> mmm@cup.portal.com (Mark Robert Thorson) writes:
>>The 386 and beyond have both device type and mask stepping numbers which
>>appear in one of the registers (DX, I believe) following reset initialization.
>Yes, this is fine and we do it. Unfortunately it gives you the added 
>problem that you need to update the ID on *every* change to the device.
>Sometimes the changes required to change the ID are more work than the
>actual bug-fix or whatever.

It's very intelligent of Intel to do this. The nice people at Inmos
are hopefully aware that all those small bug fixes can CAUSE bugs,
too.

I first encountered this idea on the PDP-9, which had an instruction
added just so that the software could tell PDP-7's from PDP-9's. The
highest flowering that I know of is on the ETA-10 system board, where
the diagnostics can check the chip type, and the chip revision level,
of everything in sight.

(For you testability types: all ~260 chips have their pins, their
control registers, and their signature analyzers, wired as a single
board-level shift register. I believe that LSSD came out of Xerox,
and signatures out of HP: thanks to them both.)
-- 
Don		D.C.Lindsay 	Carnegie Mellon School of Computer Science