Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!purdue!ames!xanth!mcnc!decvax!ima!cfisun!stellar!sporer
From: sporer@stellar.COM (Michael Sporer @stellar)
Newsgroups: comp.arch
Subject: Superscalar ISAs
Message-ID: <1989Aug22.212330.8119@stellar.COM>
Date: 22 Aug 89 21:23:30 GMT
Reply-To: sporer@stellar.com
Organization: Stellar Computer, Newton MA
Lines: 41

Hi, this is my first posting so please excuse any awkwardness or incorrect
usage. I am interested in Superscalar architectures.

We at Stellar designed our own ISA which has lots of RISC characteristics:
32 integer registers, 8 DP FP registers, single-cycle execution, delayed
branch with conditional squash (nullification). We did extend the RISC ideas
by incorporating memory operates, complex addressing (effective addressing
in the operates as well as load/store), and the incorporation of vector
operations and concurrency operations.

The vector unit operates in a load/store mode with the architecture defining
6 vector registers each with 32 DP elements.

After all this was done, we found
that not all our functional units were busy all the time so we added a
feature called packetization - which the industry now calls superscalar.
However, after much work, we found that we only get a 10 percent increase
in overall performance. We can packetize 2 integer, or 2 fp (a + and a *),
or 1 fp and 1 integer. The biggest restriction is that only one instruction
can be memory reference.

Now, I am beginning to hear about RISC chips (or chip sets) that will have
multiple functional units and an ability to examine 2,3 or even 4 instructions
for dispatch. However, there seems to be some limit (like 1.3x increase) to
the performance increase over a single functional unit.

First off, is this true. Are there really limits to our current instruction
set descriptions of programs that limit this type of parallelism?

Secondly, if this is true, is there really any work being done on true
superscalar ISAs? I am aware of the work being done by Bill Wulf at University
of Virginia (The WM Computer Architecture, Definition and Rational - Computer
Science Report No. TR-88-22, Oct 21, 1988). It seems that he has defined an
elegant method of specifying multiple memory references at once.

Anyway, I've gone on long enough. Thanks for your interest.

-- 
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Michael Sporer        uunet!stellar!sporer
Stellar Computer Inc  sporer@stellar.com