Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.csd.uwm.edu!bbn!bbn.com!slackey
From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: Superscalar ISAs
Message-ID: <44677@bbn.COM>
Date: 23 Aug 89 17:34:18 GMT
References: <1989Aug22.212330.8119@stellar.COM>
Sender: news@bbn.COM
Reply-To: slackey@BBN.COM (Stan Lackey)
Organization: Bolt Beranek and Newman Inc., Cambridge MA
Lines: 23

In article <1989Aug22.212330.8119@stellar.COM> sporer@stellar.com writes:
>We at Stellar designed our own ISA which has lots of RISC characteristics:
>We did extend the RISC ideas
>by incorporating memory operates, complex addressing (effective addressing
>in the operates as well as load/store), and the incorporation of vector
>operations and concurrency operations.

>that not all our functional units were busy all the time so we added a
>feature called packetization - which the industry now calls superscalar.
>However, after much work, we found that we only get a 10 percent increase
>in overall performance. We can packetize 2 integer, or 2 fp (a + and a *),
>or 1 fp and 1 integer.

You already have 90%? of what 'superscalar' gets in your instruction
set: mem-to-reg operations, complex addressing, and vectors.  Now, a
true RISC doesn't have those features, and so they will see very
significant improvements.  Go ahead and flame me, but that's why I say
that superscalar and CISC get the same thing, but in slightly
different ways.  Sure, superscalar is more general and according to
what I get from the posting 10% better than CISC.  But it can be more
expensive, depending upon issues like backwards compatibility.

-Stan