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From: tim@cayman.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Fast DRAMs and caches (was Re: cache speed)
Message-ID: <26964@amdcad.AMD.COM>
Date: 25 Aug 89 14:02:38 GMT
References: <AGLEW.89Aug21205533@chant.urbana.mcd.mot.com> <1989Aug24.215104.156@mentor.com>
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Reply-To: tim@amd.com (Tim Olson)
Organization: Advanced Micro Devices, Austin, TX
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In article <1989Aug24.215104.156@mentor.com> mbutts@mentor.com (Mike Butts) writes:
| Another point about caches is that many fast RISC systems, such as Apollo's
| DN10000 and the forthcoming Fujitsu SPARC-H, use separate instruction and data
| caches to accomplish two memory operations in one cycle (so-called "Harvard
| architecture").  You can't do that without caches unless you want to keep two
| copies of main memory.

Check out VRAMs (Video-DRAMs).  They have two ports to the same memory
-- a standard, random-access port, and a serial port that can be used
to read sequential data concurrently with random accesses on the other
port.




	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)