Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!amdahl!amdcad!cayman!davec From: davec@cayman.amd.com (Dave Christie) Newsgroups: comp.arch Subject: Re: Fast DRAMs and caches (was Re: cache speed) Message-ID: <26966@amdcad.AMD.COM> Date: 25 Aug 89 14:58:54 GMT References: <1989Aug24.215104.156@mentor.com> Sender: news@amdcad.AMD.COM Reply-To: davec@amd.com (Dave Christie) Organization: Advanced Micro Devices, Inc., Austin, Texas Lines: 19 Summary: Expires: Sender: Followup-To: In article <1989Aug24.215104.156@mentor.com> mbutts@mentor.com (Mike Butts) writes: > >Another point about caches is that many fast RISC systems, such as Apollo's >DN10000 and the forthcoming Fujitsu SPARC-H, use separate instruction and data >caches to accomplish two memory operations in one cycle (so-called "Harvard >architecture"). You can't do that without caches unless you want to keep two >copies of main memory. Not two copies of main memory, just one copy of multi-ported interleaved main memory. One data port, one instruction port. (While your at it, add an i/o port or two, what the hell.) You will occasionally get a conflict, depending on the degree of interleaving. Of course, this isn't necessarily cheaper than caches, certainly not as fast, and can only be justified cost-wise with very large memories. ---------- Dave Christie My opinions only, of course.