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From: slackey@bbn.com (Stan Lackey)
Newsgroups: comp.arch
Subject: Re: more Observability
Message-ID: <44797@bbn.COM>
Date: 25 Aug 89 14:35:13 GMT
References: <5945@pt.cs.cmu.edu> <21547@cup.portal.com> <1989Aug24.221628.11330@utzoo.uucp>
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Reply-To: slackey@BBN.COM (Stan Lackey)
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In article <1989Aug24.221628.11330@utzoo.uucp> henry@utzoo.uucp (Henry Spencer) writes:
>Major mistake, and not just because of R-M-W instructions.  Even some
>operations you would think would be straight writes were done with RMW
>on some Unibus CPUs.  (I can remember being very surprised to discover
>that a byte clear, I think it was, on an 11/45 was doing RMW on its
>destination.)

Yes, CLR is encoded in with a bunch of instructions that rmw a dest,
like INC, ROT, etc., and it was easier to use the same control flow and
just substitute a 'generate zeroes' ALU operation.  CLR was not
considered a performance issue.
If you needed a CLR that did just a write, you did a MOVx #0,dest.
-Stan