Path: utzoo!censor!isgtec!bmw From: bmw@isgtec.UUCP (Bruce Walker) Newsgroups: comp.arch Subject: Re: hardware complex arithmetic support (an aside) Keywords: FFT complex arithmetic Message-ID: <126@isgtec.UUCP> Date: 29 Aug 89 12:24:39 GMT References: <1672@crdgw1.crd.ge.com> <5858@pt.cs.cmu.edu> <121828@sun.Eng.Sun.COM> <3532@epimass.EPI.CO <64429@linus.UUCP> Reply-To: bmw@isgtec.UUCP (Bruce Walker) Organization: I.S.G. Technologies, Toronto, Ontario Lines: 22 In article <64429@linus.UUCP> bs@linus.UUCP (Robert D. Silverman) writes: >In article <3532@epimass.EPI.COM> jbuck@epimass.EPI.COM (Joe Buck) writes: >:It requires four multiplies, an addition, and a subtraction to do a >:complex multiply; you can do this in four cycles on the TMS320C30 by >:taking advantage of parallel multiplication and addition/subtraction. > >This is not quite correct. Usually [on most hardware] multiplies take >significantly longer than additions. Ah, but this is what makes DSP's special: if the registers are loaded, multiplies take one cycle. And since most instructions allow you to load/store/accumulate in the same cycle (as the multiply), dense instruction sequences can be created (not usually by compilers :-) where adds, subtracts and multiplies all cost the same. At least, such is the case with the tms320c25, with which I am most familiar. -- Bruce Walker ...uunet!mnetor!lsuc!isgtec!bmw "Better Living Through Connectivity" ...utzoo!lsuc!isgtec!bmw ISG Technologies Inc. 3030 Orlando Dr. Mississauga. Ont. Can. L4V 1S8