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From: tim@cayman.amd.com (Tim Olson)
Newsgroups: comp.arch
Subject: Re: Fast DRAMs and caches (was Re: cache speed)
Message-ID: <27008@amdcad.AMD.COM>
Date: 29 Aug 89 15:04:15 GMT
References: <26964@amdcad.AMD.COM> <1989Aug25.225511.828@mentor.com>
Sender: news@amdcad.AMD.COM
Reply-To: tim@amd.com (Tim Olson)
Organization: Advanced Micro Devices, Austin, TX
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In article <1989Aug25.225511.828@mentor.com> mbutts@mentor.com (Mike Butts) writes:
| From article <26964@amdcad.AMD.COM>, by tim@cayman.amd.com (Tim Olson):
| > Check out VRAMs (Video-DRAMs).  They have two ports to the same memory
| > -- a standard, random-access port, and a serial port that can be used
| > to read sequential data concurrently with random accesses on the other
| > port.
| 
| I take it you are proposing using the VRAM serial port for instruction fetches.
| That would work out fine for linear code sequences, but would cost you a full
| RAM cycle to do a branch.  Delayed branch architectures could mitigate that
| cost somewhat, but it would still cost you.  It's cheaper than a cache, but not
| as fast as a good one.  Has anyone tried using VRAMs like that in a real
| system?

There are many 29K designs that use VRAMs as main memory.  The
performance hit you note for branches is mostly ameliorated by the
29K's branch target cache.

	-- Tim Olson
	Advanced Micro Devices
	(tim@amd.com)