Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!rutgers!tut.cis.ohio-state.edu!pt.cs.cmu.edu!andrew.cmu.edu!zs04+
From: zs04+@andrew.cmu.edu (Zachary T. Smith)
Newsgroups: comp.arch
Subject: Blitter+VRAM chips (was Re: Fast DRAMs and cache)
Message-ID: <8Yzf1VW00WB50MYUcs@andrew.cmu.edu>
Date: 1 Sep 89 16:37:53 GMT
Organization: Carnegie Mellon, Pittsburgh, PA
Lines: 16


A subject really vaguely related to all this is something I remember
hearing about 2 years ago, I think.

It was the idea of putting some blit logic (logic unit, barrel shifter,
registers) inside of a VRAM chip. Instead of having a graphics processor
read out all of the bits (word by word), blit it with whatever, then
write them back in, you just put the shifting/masking/operational logic
inside of the VRAM itself. The internal blitter does only a few reads and
a  write per blit operation. Performance would be up to (for a monochrome
bitmap, 1k by 1k, 160ns/access, 3 different accesses per op) about 2 x 10^9
pixels/sec, 2 million ops/sec.
My question is, did any of the chip companies ever develop this
kind of VRAM chip?

-Zach T. Smith, zs04+@andrew.cmu.edu