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From: hascall@atanasoff.cs.iastate.edu (John Hascall)
Newsgroups: comp.arch
Subject: Filling branch delay slot with test
Message-ID: <1432@atanasoff.cs.iastate.edu>
Date: 4 Sep 89 02:33:28 GMT
Reply-To: hascall@atanasoff.cs.iastate.edu.UUCP (John Hascall)
Distribution: na
Organization: Iowa State Univ. Computation Center
Lines: 18


     I was thinking about filling the the delay slot behind
     a delayed branch and wondered if there has been any
     work/research/thought/implementations that put the
     branch instruction BEFORE the instruction that sets
     the condition codes for the branch.  For example:

         AGAIN:   JSUB   FOO_RTN        ; return FOO in R0
                  BEQL   AGAIN          ; try again if we
		  TEST   R0             ;   get zero back
		  JSUB   BAR_RTN        ; turn the FOO into a BAR

     Although not without complications, it would seem an
     excellent way to have a high branch delay slot fill ratio.
     Comments?  Flames?

John Hascall
(p.s. Sorry for discussing architecture here of all places)