Path: utzoo!attcan!utgpu!jarvis.csri.toronto.edu!mailrus!iuvax!pur-ee!hankd
From: hankd@pur-ee.UUCP (Hank Dietz)
Newsgroups: comp.arch
Subject: Re: Filling branch delay slot with test
Summary: Prefetch & Targeting
Message-ID: <12766@pur-ee.UUCP>
Date: 4 Sep 89 19:53:52 GMT
References: <1432@atanasoff.cs.iastate.edu>
Reply-To: hankd@pur-ee.UUCP (Hank Dietz)
Distribution: na
Organization: Purdue University Engineering Computer Network
Lines: 21

In article <1432@atanasoff.cs.iastate.edu> hascall@atanasoff.cs.iastate.edu.UUCP (John Hascall) writes:
>     I was thinking about filling the the delay slot behind
>     a delayed branch and wondered if there has been any
>     work/research/thought/implementations that put the
>     branch instruction BEFORE the instruction that sets
>     the condition codes for the branch.  For example:

This is called "early targeting," "branch-target buffering," or simply
instruction prefetch.  It can easily be done on a number of machines; for
example, the CARP machine design REQUIRES the user to explicitly prefetch
each instruction block (it can only execute instructions from instruction
registers).

The problem is that if you don't know the condition when you initiate the
branch, then you have to consider the branch going both ways.  This is the
primary reason that this technique isn't very popular.  A more popular
alternative is to get around the one-condition-code-register code motion
constraint by having multiple condition registers (e.g., using general
registers for condition evaluation).

						-hankd@ecn.purdue.edu