Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!ames!apple!voder!pyramid!prls!mips!wilkes
From: wilkes@mips.COM (John Wilkes)
Newsgroups: comp.arch
Subject: Re: SRAM vs. DRAM, 33MHz 386 UNIX-PC
Message-ID: <27133@proton.mips.COM>
Date: 8 Sep 89 00:28:33 GMT
References: <21936@cup.portal.com> <7851@cbmvax.UUCP>
Reply-To: wilkes@mips.COM (John Wilkes)
Organization: MIPS Computer Systems, Sunnyvale, CA
Lines: 24

In article <7851@cbmvax.UUCP> daveh@cbmvax.UUCP (Dave Haynie) writes:
>
  {talking about flushing the cache}

>MUST between user tasks, since the address spaces are aliased.  Caching still
                                
i believe that this is true only for a virtual cache.  a physical cache
does not have the aliasing problem.

>> Harvard A.(separate data/instruction cache), 
>
>This isn't an advantage as an external cache unless you're CPU has external
>I and D busses.  The only one I know of that does is the Motorola 88100.  While

not necessarily.  you might want your d cache to have a 128-byte line, and
your i cache to have an eight byte line, for example.  code references and
data references usually have different access patterns.

doesn't the amd 29000 have external i and d busses?  it's been a long time
since i looked at that chip...
-- 
-wilkes

wilkes@mips.com   -OR-   {ames, decwrl, pyramid}!mips!wilkes