Path: utzoo!utgpu!jarvis.csri.toronto.edu!mailrus!csd4.csd.uwm.edu!uakari.primate.wisc.edu!ames!vsi1!wyse!mips!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: Parity in Internal Data Paths of Processors
Message-ID: <27196@winchester.mips.COM>
Date: 8 Sep 89 23:54:12 GMT
References: <124311@sun.Eng.Sun.COM> <34595@apple.Apple.COM>
Reply-To: mash@mips.COM (John Mashey)
Organization: MIPS Computer Systems, Inc.
Lines: 22

In article <34595@apple.Apple.COM> baum@apple.UUCP (Allen Baum) writes:
>[]
.....
>I think that most of the large IBM mainframes have parity on registers and
>data-paths, but I dont have strong information. Carrying parity through the
........

We don't do them on internal datapaths.  RX000 CPUs do generate and
check parity for the caches, and they call a parity error a cache-miss,
but then set a CPU staus register bit that can be checked occasionally
by the kernel to see if something is failing.

There are also modes in the cache control to:
	isolate the caches
	write data with bad parity into the cache
	read the cache, and get a parity-right versus parity-wrong bit,
	so you can test the parity circuits.
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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